On Effective Computation with Single Electron Tunnelling Devices

It is generally accepted that fundamental physical limitations will eventually inhibit further (C)MOS feature size reduction. Several emerging nano-electronic technologies with greater scaling potential, such as Single Electron Tunnelling (SET), are currently under investigation. Each of those exhibits its own switching behavior, resulting in new paradigms for logic design and computation. This paper presents an analysis of various design styles that might be potentially utilized in conjunction with SET devices. We discuss and compare three different SET designs styles as follows: CMOS-alike logic, based on SET transistors; Single Electron Encoded Logic, based on threshold gates that utilize the intrinsic behavior of SET tunnel junctions; Electron Counting logic, based on direct encoding of integers as charge combined with computation via charge transport. Our analysis clearly indicate that the last two approaches are more promising as they make a better use of the specific properties and behavior of